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1 low voltage or-ing fet controller isl6146 the isl6146 represents a family of or-ing mosfet controllers capable of or-ing voltages from 1v to 18v. together with suitably sized n-channel power mosfets, the isl6146 increases power distribution efficiency when replac ing a power or-ing diode in high current applications. it provid es gate drive voltage for the mosfet(s) with a fully integrated charge pump. the isl6146 allows users to adjust with external resistor(s) the v out - v in trip point, which adjusts the control sensitivity to system power supply noise. an open drain fault pin will indicate if a conditional or fet fault has occurred. the isl6146a and isl6146b are optimized for very low voltage operation, down to 1v with an a dditional independent bias of 3v or greater. the isl6146c provides a voltage compliant mode of operation down to 3v with programmable undervoltage lock out and overvoltage protecti on threshold levels the isl6146d and isl6146e are like the isl6146a and isl6146b respectively but do not have co nduction state reporting via the fault output . features ? or-ing down to 1v and up to 20v with isl6146a, isl6146b, isl6146d and isl6146e ? programmable voltag e compliant operation with isl6146c ? vin hot swap transient protection rating to +24v ? high speed comparator provides fast <0.3s turn-off in response to shorts on sourcing supply ? fastest reverse current fault isolation with 6a turn-off current ? very smooth switching transition ? internal charge pump to drive n-channel mosfet ?user programmable v in - v out vth for noise immunity ? open drain fault output with delay - short between any two of the or-ing fet terminals - gate voltage and excessive fet v ds - power-good indicator (isl6146c) ? msop and dfn package options applications ? n+1 industrial and telecom power distribution systems ? uninterruptable power supplies ? low voltage processor and memory ?storage and datacom systems table 1. key differences between parts in family part number key differences isl6146a separate bias and vi n with active high enable isl6146b separate bias and vin with active low enable isl6146c vin with ovp/uvlo inputs isl6146d isl6146a wo conduction monitor & reporting isl6146e isl6146b wo conduction monitor & reporting figure 1. typical application figure 2. isl6146 gate high current pull-down vin gate vout gnd adj + - + vout + - + c o m m o n p o w e r b u s q1 isl6146b flt bias voltage dc/dc voltage dc/dc en (3v - 20v) (3v - 20v) q2 c o m m o n p o w e r b u s vin gate vout gnd adj isl6146b flt bias en gate fast off, ~200ns fall time ~70ns from 20v to 12.6v across 57nf gate output sinking ~ 6a april 26, 2013 fn7667.4 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2011-2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl6146 2 fn7667.4 april 26, 2013 block diagram pin configuration isl6146 (8 ld msop/dfn) top view + + vin vout adj flt gate bias 4a 8ma high speed comparator q-pump vds forward regulator reverse detection comparator enable + fault diagnostic 1. v in - v out > 570mv 2. gate - v in < 220mv (a,b,c only) 3. temp > +150c 4. v bias < por (isl6146a/b/d/e) 5. v in or v out < por (isl6146c) + - + - 19mv 57mv * connected to bias on isl6146a/b/d/e * connected to vout on isl6146c enable + - v ref en/en isl6146a/b/d/e + - v ref ovp isl6146c en uvlo + + 6. v in < v out 7. gate to drain and gate to source shorts isl6146a, isl6146b, isl6146d, isl6146e isl6146c vin gate fault vout adj en isl6146a/d bias gnd en isl6146b/e 1 2 3 4 8 7 6 5 vin gate fault vout adj gnd uvlo ovp 1 2 3 4 8 7 6 5 epad on dfn only, connect to gnd pin descriptions msop/ dfn symbol description 1 gate gate drive output to the external n-channel mosfet generated by the ic internal charge pump. gate turn-on time is typicall y <1ms. allows active control of external n-ch annel fet gate to perform or-ing function. the gate drive is between v in + 7v at v in = 3.3v and v in +12v at v in = 18v. 2 vin connected to the sourcing supply side (or-ing mosfet source ), this pin serves as the sense pin to determine the or?d supply voltage. the or-ing mosfet will be turned off when v in becomes lower than v out by a value more than the externally set threshold or the defaulted intern al threshold. range: 0v to 24v 3 isl6146a isl6146b isl6146d isl6146e bias primary bias pin. connected to an independent voltag e supply greater than or equal to 3v and greater than v in . range: 3.0 to 24v 3 isl6146c uvlo programmable uvlo protection to prevent premature turn-o n prior to vin being adequately biased. range: 0v to 24v 4 isl6146a isl6146d en active high enable input to turn on the fet. internally pulled low to gnd through 2m ? . range: 0v to 24v
isl6146 3 fn7667.4 april 26, 2013 4 isl6146b isl6146e en active low enable input to turn on the fet. internally pulled high to bias through 2m ? . range: 0 to 24v 4 isl6146c ovp programmable ov protection to prevent continued operation when the monitored voltage is too high. a back-to-back fet configuration must be employed to implement the ovp capability. range: 0v to 24v 5 gnd chip ground reference. 6fault open-drain pull-down fault indicating outp ut with internal on chip filtering (t flt ). the isl6146 fault detection circuitry pulls down this pin to gnd as it detects a fault or a disabled input (en = ?0? or en = ?1?). different types of faults and their detection mechanisms are discussed in more detail on page 17. these faults include: a. gate is off (gate < v in +0.2v) when enabled [this condition is not reported on the isl6146d and isl6146e] b. v in -v out > 0.57v when on. c. fet g-d or g-s or d-s shorts. d. v in < por l2h e. v in < v out f. over-temperature range: 0 to v out 7 adj resistor programmable v in - v out voltage threshold (vth) of the high speed comparator. this pin is either directly connected to vout or can be connected through a 5k ? to 100k ? resistor to gnd. allows for adjusting the voltage difference threshold to prevent unintended turn-off of the pa ss fet due to normal system voltage fluctuations. range: 0.4 to v out 8 vout the second sensing node for external fet control and conn ected to the load side (or-in g mosfet drain). this is the common connection point for multiple paralleled supplies. v out is compared to v in to determine when the or-ing fet has to be turned off. range: 0v to 24v pad thermal pad connect to gnd pin descriptions (continued) msop/ dfn symbol description ordering information part number (notes 1, 2, 3) part marking temp range (c) package (pb-free) pkg. dwg. # isl6146afuz 6146a -40 to +125 8 ld msop m8.118 isl6146afuz-t 6146a -40 to +125 8 ld msop tape and reel m8.118 isl6146afuz-t7a 6146a -40 to +125 8 ld msop tape and reel m8.118 isl6146afuz-tk 6146a -40 to +125 8 ld msop tape and reel m8.118 isl6146afrz 46af -40 to +125 8 ld 3x3 dfn l8.3x3j isl6146afrz-t 46af -40 to +125 8 ld 3x3 dfn tape and reel l8.3x3j ISL6146AFRZ-T7A 46af -40 to +125 8 ld 3x3 dfn tape and reel l8.3x3j isl6146afrz-tk 46af -40 to +125 8 ld 3x3 dfn tape and reel l8.3x3j isl6146bfuz 6146b -40 to +125 8 ld msop m8.118 isl6146bfuz-t 6146b -40 to +125 8 ld msop tape and reel m8.118 isl6146bfuz-t7a 6146b -40 to +125 8 ld msop tape and reel m8.118 isl6146bfuz-tk 6146b -40 to +125 8 ld msop tape and reel m8.118 isl6146bfrz 46bf -40 to +125 8 ld 3x3 dfn l8.3x3j isl6146bfrz-t 46bf -40 to +125 8 ld 3x3 dfn tape and reel l8.3x3j isl6146bfrz-t7a 46bf -40 to +125 8 ld 3x3 dfn tape and reel l8.3x3j isl6146bfrz-tk 46bf -40 to +125 8 ld 3x3 dfn tape and reel l8.3x3j isl6146cfuz 6146c -40 to +125 8 ld msop m8.118
isl6146 4 fn7667.4 april 26, 2013 isl6146cfuz-t 6146c -40 to +125 8 ld msop tape and reel m8.118 isl6146cfuz-t7a 6146c -40 to +125 8 ld msop tape and reel m8.118 isl6146cfuz-tk 6146c -40 to +125 8 ld msop tape and reel m8.118 isl6146cfrz 46cf -40 to +125 8 ld 3x3 dfn l8.3x3j isl6146cfrz-t 46cf -40 to +125 8 ld 3x3 dfn tape and reel l8.3x3j isl6146cfrz-t7a 46cf -40 to +125 8 ld 3x3 dfn tape and reel l8.3x3j isl6146cfrz-tk 46cf -40 to +125 8 ld 3x3 dfn tape and reel l8.3x3j isl6146dfuz 6146d -40 to +125 8 ld msop m8.118 isl6146dfuz-t 6146d -40 to +125 8 ld msop tape and reel m8.118 isl6146dfuz-t7a 6146d -40 to +125 8 ld msop tape and reel m8.118 isl6146dfuz-tk 6146d -40 to +125 8 ld msop tape and reel m8.118 isl6146dfrz 46df -40 to +125 8 ld 3x3 dfn l8.3x3j isl6146dfrz-t 46df -40 to +125 8 ld 3x3 dfn tape and reel l8.3x3j isl6146dfrz-t7a 46df -40 to +125 8 ld 3x3 dfn tape and reel l8.3x3j isl6146dfrz-tk 46df -40 to +125 8 ld 3x3 dfn tape and reel l8.3x3j isl6146efuz 6146e -40 to +125 8 ld msop m8.118 isl6146efuz-t 6146e -40 to +125 8 ld msop tape and reel m8.118 isl6146efuz-t7a 6146e -40 to +125 8 ld msop tape and reel m8.118 isl6146efuz-tk 6146e -40 to +125 8 ld msop tape and reel m8.118 isl6146efrz 46ef -40 to +125 8 ld 3x3 dfn l8.3x3j isl6146efrz-t 46ef -40 to +125 8 ld 3x3 dfn tape and reel l8.3x3j isl6146efrz-t7a 46ef -40 to +125 8 ld 3x3 dfn tape and reel l8.3x3j isl6146efrz-tk 46ef -40 to +125 8 ld 3x3 dfn tape and reel l8.3x3j isl6146aeval1z isl6146a evaluation board (if desired with isl6146d, please contact support) isl6146beval1z isl6146b evaluation board (if de sired with isl6146e, please contact support) isl6146ceval1z isl6146c evaluation board isl6146deval1z 1 pair of isl6146d mini development boar ds (if desired with isl6146a, please contact support) isl6146eeval1z 1 pair of isl6146e mini development boar ds (if desired with isl61 46b, please contact support) notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl6146 . for more information on msl please see techbrief tb363 . ordering information (continued) part number (notes 1, 2, 3) part marking temp range (c) package (pb-free) pkg. dwg. #
isl6146 5 fn7667.4 april 26, 2013 table of contents absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 typical performance curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 power-up considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 typical applications circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 isl6146 evaluation platforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 description and use of the evaluation boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 l8.3x3j. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 m8.118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
isl6146 6 fn7667.4 april 26, 2013 absolute maximum rating s thermal information bias, vin, vout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +24v gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 40v en, en , uvlo, ovp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +24v adj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v out fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v out esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . .2.5kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 250v latch up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) msop package (notes 4, 7) . . . . . . . . . . . . 140 41 dfn package (notes 5, 6) . . . . . . . . . . . . . . 46 5 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c recommended operating conditions bias supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3v to +20v or?d supply voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1v to bias temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 6. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 7. for jc , the ?case temp? location is taken at the package top center electrical specifications v cc = bias = 12v, unless otherwise stated. t a = +25c to +85c. boldface limits apply over the operating temperature range, -40c to +125c. symbol parameters test conditions min (note 8) typ max (note 8) units bias por l2h por rising bias rising, gate rising 1.9 2.5 2.95 v por hys por hysteresis 189 mv ibias_en_18 isl6146a/b/d/e bias current bias, v in = 18v, adj, v out = 16.98v, enabled 3.6 5 ma ivin_en_18 isl6146a/b/d/e v in current bias, v in = 18v, adj, v out = 16.98v, enabled 25 40 a ivin_en_18 isl6146c v in current v in = 18v, adj, v out = 16.98v, enabled 3 4.5 ma ivout_en_18 isl6146a/b/d/e v out current bias, v in = 18v, v out = 16.98v, enabled 14 20 a vout_en_18 isl6146c v out current v in = 18v, v out = 16.98v, enabled 400 500 a ibias_den_18 isl6146a/b/d/e bias current bias, v in = 18v, adj, v out = 16.98v, disabled 1.7 3 ma ivin_den_18 isl6146a/b/d/e v in current bias, v in = 18v, adj, v out = 16.98v, disabled 27 37 a ivin_den_18 isl6146c v in current v in = 18v, adj, v out = 16.98v, disabled 1.3 1.5 ma ivout_den_18 isl6146a/b/d/e v out current bias, v in = 18v, v out = 16.98v, disabled 14 20 a ivout_den_18 isl6146c v out current v in = 18v, v out = 16.98v, disabled 385 500 a t bias2gte bias to gate delay bias > por l2h to gate rising 150 210 s gate v gh_3 charge pump voltage v in , bias = 3v v in - v out > v fwd_vr v in +5v v in +7v v in +10.5v v v gh_12 charge pump voltage v in , bias = 12v v in - v out > v fwd_vr v in +9v v in +10v v in +17.5v v v gh_18 charge pump voltage v in , bias = 18v v in - v out > v fwd_vr v in +9v v in +10v v in +18v v v gl low voltage level v in - v out < 0v 0 0.1 v i pdl low pull-down current v in = 12v, v out = 12.2v adj = 11v 5 8.4 13 ma i pdh high pull-down current v in falling from 12v to 10v in 2s 3.5 6.5 a t toff fast turn-off time v in = v bias = 12v, v gate = 18v to 10v, c gate = 57nf 65 130 ns
isl6146 7 fn7667.4 april 26, 2013 t toffs slow turn-off time v in = v bias = 12v, v gate = 18v to 10v, c gate = 57nf 58 80 s i on turn-on current bias = 12v, vg = 0v 1 ma bias = 12v, vg = 20v 0.15 ma v vg_fltr gate to v in rising fault voltage gate > v in , enabled, flt output is high. (does not apply to isl6146d and isl6146e) 320 440 560 mv v vg_fltf gate to v in falling fault voltage gate > v in , enabled, flt output is low. (does not apply to isl6146d and isl6146e) 140 220 300 mv control and regulation i/o v rr reverse voltage detection rising v out threshold v out rising 35 57 79 mv v rf reverse voltage detection falling v out threshold v out falling 10 30 51 mv t rs reverse voltage detection response time 10 s v fwd_vr amplifier forward voltage regulation isl6146 controls voltage across fet v ds to v fwd_vr during static forward operation at loads resulting in id*r ds(on) < v fwd_vr 11 19 28 mv v os_hs hs comparator input offset voltage -14 0.7 14 mv v th(hs5k) adj adjust threshold with 5k to gnd r adj = 5k ? to gnd 0.57 0.8 1.1 v v th(hs100k) adj adjust threshold with 100k to gnd r adj = 100k ? to gnd 10 40 95 mv t hspd hs comparator response time v out > v in , 1ns transition, 5v differential 170 ns v fwd_flt v in to v out forward fault voltage v in > v out , gate is fully on, flt output is low 330 450 570 mv v fwd_flt_hys v in to v out forward fault voltage hysteresis v in > v out , gate is fully on, flt output is high 44 mv fault output i flt_sink fault sink current bias = 18v fault = 0.5v, v in < v out , v gate = v gl 5 9ma i flt_leak fault leakage current fault = ?v flt_h ?, v in > v out , v gate = v in + v gqp 0.04 10 a t flt_l2h fault low to high delay gate = v gqp to fault output is high 10 23 s t flt_h2l fault high to low delay gate = v in to fault output is low 1.7 3 s enable uvlo/ovp/adj inputs vthra isl6146a/d en rising vth 580 606 631 mv vthr_hysa isl6146a/d en vth hysteresis -90 mv vthfb isl6146b/e en falling vth 580 606 631 mv vthf_hysb isl6146b/e en vth hysteresis +90 mv vthfc isl6146c ovp falling vth 580 606 631 mv vthf_hysc isl6146c ovp vth hysteresis +90 mv vthrc isl6146c uvlo rising vth 580 606 631 mv vthr_hysc isl6146c uvlo vth hysteresis -90 mv t en2gter en/uvlo rising to gate rising delay 10 12 s en /ovp falling to gate rising delay 9 12 s electrical specifications v cc = bias = 12v, unless otherwise stated. t a = +25c to +85c. boldface limits apply over the operating temperature range, -40c to +125c. (continued) symbol parameters test conditions min (note 8) typ max (note 8) units
isl6146 8 fn7667.4 april 26, 2013 t en2gtef en/uvlo falling to gate falling delay 2 4 s en /ovp rising to gate falling delay 2 4 s ren_h enable pull-down resistor isl6146a, isl6146d 2 m ? ren_l enable pull-up resistor isl6146b, isl6146e 2 m ? vadj adj pin voltage r adj 5k ? to 100k ? 0.4 v radj adj pull-up resistor internal adj pull-up resistor to v out 3.85 m ? ots over-temperature sense fault signals in operation 140 c ots hys over-temperature sense hysteresis 20 c hts high temperature sense fault signals upon enabling 125 c note: 8. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. electrical specifications v cc = bias = 12v, unless otherwise stated. t a = +25c to +85c. boldface limits apply over the operating temperature range, -40c to +125c. (continued) symbol parameters test conditions min (note 8) typ max (note 8) units
isl6146 9 fn7667.4 april 26, 2013 typical performance curves figure 3. isl6146a/b/d/e bias and isl6146c v in current vs temperature figure 4. isl6146a/b/c/d/e v in and v out current vs temperature figure 5. gate voltage vs temperature figure 6. por vth rising and falling voltage figure 7. isl6146a/d en vth vs temperature f igure 8. isl6146b/e en vth vs temperature 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -40 25 85 125 temperature (c) i bias /iv in current (ma) 18v disabled 12v disabled 3v disabled 18v enabled 12v enabled 3v enabled temperature (c) 40 35 30 25 20 15 10 -40 25 85 125 18v disabled 12v disabled 3v disabled v in /v out current (ma) v out current v in current 3v enabled 18v enabled 12v enabled 0 5 10 15 20 25 30 35 -40 25 85 125 temperature (c) hard on gate voltage (v) bias = 3v bias = 12v bias = 18v temperature (c) v por vth (v) 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 -40 25 85 125 por vth falling por vth rising 0.40 0.45 0.50 0.55 0.60 0.65 0.70 -40 25 85 125 temperature (c) en vth (v) en assert rising vth en deassert falling vth temperature (c) en vth (v) 0.54 0.56 0.58 0.60 0.62 0.64 0.66 0.68 0.70 0.72 0.74 -40 25 85 125 en deassert rising vth en assert falling vth
isl6146 10 fn7667.4 april 26, 2013 figure 9. isl6146c uvlo/ovp vth vs temp erature figure 10. gate turn-on current v in = 12v figure 11. gate hard turn-off current figure 12. gate slow turn-off current figure 13. increasing reverse voltage detectio n vth figure 14. reverse voltage response time typical performance curves (continued) temperature (c) ovp and uvlo vth (mv) 450 500 550 600 650 700 750 -40 25 85 125 uvlo falling uvlo rising and ovp falling ovp rising temperature (c) gate turn-on current (ma) 0.1 0.3 0.5 0.7 0.9 1.1 1.3 -40 25 85 125 vg = 0v temperature (c) gate pull-down current (a) 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 -4025 85125 temperature (c) gate pull-down current (ma) 0 1 2 3 4 5 6 7 8 9 10 -40 25 85 125 temperature (c) reverse detection voltage (mv) 52.0 52.5 53.0 53.5 54.0 54.5 55.0 55.5 56.0 -40 25 85 125 temperature (c) response time (s) 15 20 25 30 35 40 45 -4025 85125
isl6146 11 fn7667.4 april 26, 2013 figure 15. high speed comparator offset voltage f igure 16. high speed comparator response time figure 17. hs comparator adjustable vth figure 18. en/en /ovp/uvlo vth delta vs bias voltage normalized to bias = 12v figure 19. forward voltage regulation figure 20. v in to v out forward fault voltage typical performance curves (continued) temperature (c) offset voltage (mv) -3 -2 -1 0 1 2 3 -40 25 85 125 temperature (c) response time (ns) 100 120 140 160 180 200 220 240 260 280 300 -40 25 85 125 0 100 200 300 400 500 600 700 800 900 -40 25 85 125 temperature (c) hs comp adjust v th ( mv ) r adj to gnd = 5k ? r adj to gnd = 100k ? bias voltage (v) relative % 0.993 0.994 0.995 0.996 0.997 0.998 0.999 1.000 1.001 1.002 31218 temperature (c) v in to v out fwd voltage reg ( mv ) 19.0 19.2 19.4 19.6 19.8 20.0 20.2 20.4 20.6 20.8 21.0 -40 25 85 125 temperature (c) v in - v out fault v th ( mv ) 420 425 430 435 440 445 450 455 460 465 -40 25 85 125
isl6146 12 fn7667.4 april 26, 2013 figure 21. isl6146c slow ramp connect 12v or-ing figure 22. isl6146c slow ramp disconnect 12v or-ing figure 23. isl6146c hot swap connect 12v or-i ng figure 24. isl6146c hot disconnect 12v or-ing figure 25. i sl6146a/d en/isl6146c uvlo to gate on delay figure 26. isl6146a/d en/isl6146c uvlo to gate off delay typical performance curves (continued) gate1 gate 2 iin1 iin2 gate1 gate 2 iin1 iin2 gate1 gate 2 iin1 iin2 gate1 gate 2 iin1 iin2 gate en/uvlo en/uvlo gate
isl6146 13 fn7667.4 april 26, 2013 figure 27. isl6146b/e en to gate on delay figure 28. isl6146b/e en to gate off delay figure 29. isl6146c ovp to gate on delay figure 30. isl6146c ovp to gate off delay figure 31. isl6146c rising v in , uvlo and ovp function figure 32. isl6146c falling, v in ovp and uvlo function typical performance curves (continued) en gate en gate ovp gate ovp gate gate vin v in rising through both the programmed uvlo and ovp levels. gate turns-on as v in exceeds 10v then turns-off as v in exceeds 15v gate vin v in falling through both the programmed ovp and uvlo levels. gate turns-on as v in > 13v then turns-off as v in > 8.3v
isl6146 14 fn7667.4 april 26, 2013 figure 33. back-to-back fet turn_on de tail figure 34. isl6146 rising por vth figure 35. fast gate turn-off with 57nf gate figure 36. response to v in shorted to gnd with adj shorted to v out figure 37. response to v in shorted to gnd with adj 5k ? to gnd figure 38. response to v in shorted to gnd with adj 100k ? to gnd typical performance curves (continued) gate vin vout gate vin vout vin gate vin rising to <2.5v when gate becomes active gate fast off, ~200ns fall time ~70ns from 20v to 12.6v across 57nf gate output sinking ~ 6a vout gate1 vin1 shorted to gnd gate2 high speed comparator vth = v os(hs) vout gate1 vin1 shorted to gnd gate2 high speed comparator vth = 800mv vout gate1 vin1 shorted to gnd gate2 high speed comparator vth = 40mv
isl6146 15 fn7667.4 april 26, 2013 figure 39. v in hot swapped to gate with bias = 12v no load figure 40. fault asserting v in to v out > v fwd_flt figure 41. high speed comp arator offset voltage distribution figure 42. forward regulation voltage distribution figure 43. reverse detection rising voltage distribution figure 44. fast ramp reverse protection timing diagram typical performance curves (continued) ? vin gate vin - vout flt vin vout hs comp adjust v th (mv) % of distribution 0 5 10 15 20 25 30 35 -101234567 0 5 10 15 20 25 30 35 40 17 18 19 20 21 22 % of distribution v fwd_vr (mv) 0 5 10 15 20 25 30 35 40 50 52 54 56 58 60 62 64 66 68 vrr (mv) % of distribution v ds 0v + v r 20v 12.6v v gate t hspd t off v bias = v in = 12v
isl6146 16 fn7667.4 april 26, 2013 figure 45. isl6146a flt response to non-conduction figure 46. isl6146d flt response to non-conduction typical performance curves (continued) flt gate vin vin gate flt
isl6146 17 fn7667.4 april 26, 2013 functional description functional overview in a redundant power distribution system, similar potential and parallel power supplies each contribute to the load current through various active and passi ve current sharing schemes. typically or-ing power diodes are used to protect against reverse current flow in the event that one of the power supplies falls below the common bus voltage or develops a catastrophic failure. however, using a discrete or-ing diode solution has some significant drawbacks. the primary downside is the increased power dissipation loss in the or-ing diodes as system power requirements increase. at the lowest voltages where the isl6146 is designed for use, the voltag e distribution losses across an or-ing diode can be a signific ant percentage, in some cases approaching 70%. another disadvantage when using an or-ing diode is failure to detect a shorted or opened current path, which jeopardizes system power availability and reliability. an open diode may reduce the system to a single point of failure while a shorted diode eliminates the system?s power protection. using an active or-ing fet contro ller, such as the isl6146, helps with these potential issues. the use of a low on-resistance fet as the or-ing component allows for a more efficient system design as the voltage across the fet is much lower than that across a forward biased diode. additionally, the isl6146 has a dedicated fault (fault ) output pin that indicates when there is a conditional or fet fault short providing the di agnostic capability that a diode is unable to. the isl6146 is designed to or to gether voltages as low as 1v when supplied with a separate bias supply of 3v or greater. otherwise, the isl6146 is designed to be biased from and or voltages across the 3v to 20v nominal supply range. in a single fet configuration as voltage is first applied to a vin pin, the fet body diode conducts providing all the isl6146s connected on a common bus circuit, bias via the vout pins. as individual power supply voltages ramp up in excess of the rising por threshold, the isl6146?s inte rnal charge pump activates to provide a floating gate drive voltage for the external n-channel or-ing mosfet, thus turning the fets on once v in > v out . the isl6146 continuously monitors the drain and source of the or-ing fet and provides a reverse voltage (n-channel mosfet v out - v in ) detection threshold (vr) that, when exceeded, indicates a reverse current condition. once this threshold is exceeded, the isl6146 turns off the or-ing fet by pulling down the gate pin to gnd. the isl6146 also provides high speed v out > v in transient protection as in the case of a catastrophic vin failure. the isl6146 additionally provides for adjustment of the v in - v out reverse voltage vth(vr vth) via the adj pin of the isl6146 with an external resistor to gnd. this allows adjusting the v in - v out voltage threshold level to compensate for normal system voltage fluctuations, thus eliminating unnecessary reaction by the isl6146. the total v in - v out vr vth is the sum of both the internal offset and the external programmed vr vth. in the event of a v out > v in condition, the isl6146 responds either with a high or low current pull-down on the gate pin depending on whether the high speed comparator (hscomp) has been activated or not. the hscomp determines if the vr occurred within 1 s, by continuously monitoring the fet vds and if so, the high pull-down current is used to turn off the or-ing fet. in the event of a falling vin transition in <1 s, (i.e., a catastrophic failure of the power source) the hscomp protects the common bus from the individual faulted power supply short by turning off the shorted supply?s or-ing mosf et in less than 300ns, ensuring the integrity of the common bus voltage from reverse current to the damaged supply. once the correct v in > v out relationship is established again, the isl6146 again turns on the fet. the fault pin is an open drain, ac tive low output indicating that a fault or specific condition has occurred, these include: ? gate is off (gate < v in +0.2v). lack of conduction, not a fault, just not on. isl6146d and isl6146e do not respond to this condition ? faults resulting in v in - v out > 0.57v when on ? an open fet resulting in body diode conduction ? excessive current through fet ? fet faults monitored and reported include - g-d, gate unable to drive to q-pump voltage - g-s, gate unable to drive to q-pump voltage - d-s shorts, when gate is off vds < 2v -v in < por - missing v in -v in shorted to gnd on the isl6146c version, a conditional fault is also signalled if the v in is not within the programmed uvlo and ovp levels. the isl6146 has an on-chip over-temperature fault threshold of ~+140c with a 20c hysteresis . although the isl6146 itself produces little heat, it senses the environment in which it is, likely including a close by fet. the isl6146a/d and isl6146b/e are functional variants with an enabling input of either polarity. this feature is used when the need to interrupt the current path via signaling is necessary. this is accomplished by implementing two fets in series so that there is a body diode positioned to block current in either direction. this functionality is considered an additional enhancement to the or-ing diode it replaces. the isl6146c employs the use of a programmable undervoltage lock out (uvlo) and a programmabl e overvoltage protection (ovp) input. this allows the gate to only turn-on when the monitored voltage is between the programmed lower and upper levels. this application would use the back-to-back fet configuration. in the event that the current path does no t need to be interrupted then the en, uvlo and ovp inputs can all be overridden. the isl6146d and isl6146e are variants of the isl6146a and isl6146b respectively, the difference being the former do not respond to a nonconduction condition (when enabled and vin>vout, the gate is not on) unlike the latter that do signal afault.
isl6146 18 fn7667.4 april 26, 2013 applications information power-up considerations bias and v in constraints upon power-up when the v in supply is separate from the bias supply, the bias voltage must be greater or equal to the v in voltage at all times. when using a single supply for both the isl6146 bias and the or-ing supply, the v in and bias pins can be configured with a low value resistor between the two pins to provide some isolation and decoupling to support the chip bias even as the or?d supply experiences voltage droops and su rges. although not necessary to do so, it is a best design practice for particularly noisy environments. fet to ic layout recommendations connections from the fet(s) to the isl6146 vin and vout pins must be kelvin in nature and as close to the fet drain and source pcb pads as possible to eliminat e any trace resistance errors that can occur with high currents. this connection placement is most critical to providing the most accurate voltage sensing particularly when the back-to-ba ck fet configuration is used. likewise, connections from ovp, uv lo and adj are also critical to optimize accuracy. adjusting the hs comparator reverse voltage threshold the isl6146 allows adjustment of the hs comparator reverse voltage detection threshold (vr vth), the difference in v out - v in . there are two valid adj pin configurations: 1. adj connected to vout: this makes the hs comparator threshold equal to the intrinsic error in the hs comparator input. this is the default condition and the most likely used configuration. 2. a single resistor is connect ed from adj pin to ground: making the hs compar ator threshold = v out - 4k/r adj . so, for a 100k ? r ext , hs comparator thre shold = 40mv below vout and for a 5k ? r ext hs comparator threshold = ~ 800mv below vout. the recommended resistor range is 5k ? to 100k ? for this voltage adjustment. at power-up, the hs comparator threshold is default set to the internal device error first, and then released to the user programmed threshold after the related circuits are ready. it takes ~20 s for the circuit to switch from the default setting to the user programmed threshold after a por startup. the current out of the adj pin with a resistor to gnd is equal to 0.4v/r ext. back-to-back fet configuration when using the back-to-back fet configuration, the fet choice must be such that the voltage ac ross both fets at full current loading be less than the minimum forward voltage fault threshold of 400mv to avoid unintended fault notification. in this configuration, it may be tempting to use the enable inputs to force a path by switching between the two as opposed to having both paths on, and having the higher voltage source provide current. the problem with that is the timing of the fets on and off, so that excessive v out voltage droop is not introduced if the turn-off happens faster, or before the (or a slower) turn-on momentarily leaves the load with an inadequate power connection. typical applications circuits there are four basic configurat ions that the isl6146 can be used in: 1. for voltages >3v where the bias and v in are common 2. for a very low or-ing voltage, <3v operation, bias >3v 3. for a voltage window compliant operation and, 4. for a signaled operation where the current path is controlled by an input signal or minimum voltage condition. each of these configurations ca n be tailored for the high speed comparator (hs comp) reverse threshold via the adj input being connected either to vout or to gnd via a resistor as previously explained. additionally, the voltag e window is adjustable for both a minimum and maximum operating voltage via the uvlo and ovp inputs and a resistor divider also explained earlier. also, soft-start and turn-on and turn-off characteristics can be tailored to suit. the three evaluation platforms provided demonstrate the four basic configurations and provide for the additional tailoring of the various performance characteristics. vin gate vout gnd adj very low + - + c o m m o n p o w e r b u s q1 vin gate vout gnd adj + - + c o m m o n p o w e r b u s isl6146a isl6146a flt flt bias bias dc - dc voltage bias voltage >3v en en (1v-3v) q2 figure 47. low voltage application diagram very low dc - dc voltage (1v-3v)
isl6146 19 fn7667.4 april 26, 2013 the figure 1 circuit shown on page 1 is the basic circuit used for or-ing voltages >3v to 20v. the isl6146a application shown in figure 47 is the configuration for or-ing very low voltages of 1v to 3v. additionally, this application shows the utilization of the adj input with a single resistor tied to gnd. this provides the user a programmable level of v out > v in before the high speed (hs) comparator is activated and the gate output is pulled down to allow for normal voltage fluctuations in the system. notice that in both of these circuits, the en or en inputs are defaulted to enabled and have no current path on/off control. failure to do so correctly will resu lt in only body diode conduction and a resulting fault indication. the v in and v out to fet and gnd to adj connections are drawn to emphasize the kelvin connec tion necessary to correctly monitor the voltage across the fet, and for the vr vth monitor to eliminate any stray resistance effects. the isl6146c application shown in figure 48 is limited to the 3v to 20v v in range and must implement the back-to-back fet configuration to utilize the uvlo and ovp inputs and capabilities. as the v in voltage rises above the minimum programmed voltage, the related or-ing fets will turn on and stay on until either the minimum voltage requirement is no longer met or the v in voltage exceeds its programmed maximum. the minimum and maximum programmed voltage levels are done with the resistor divider on the uvlo and ovp pins. these levels should be programmed to take into account conduction path losses to the load in addition to the ic operational constraints. when using the back-to-back fet configuration, the user must chose fets to ensure (2r ds(on) + pcb ir) i load <0.5v to avoid tripping the v in - v out > 0.5v when on fault. the application diagram in figu re 49 shows the isl6146a or isl6146b utilizing the en or en pin as a signalled input to open or close the conduction path fr om power supply to load. this feature can be implemented on or-ing 1v to 20v but is shown for or-ing <3v. the enable input signaling can be simultaneous across the n+1 number of isl6146s used. although not needed for thermal relief, connect the dfn epad to gnd. switch-over circuits switch over applications are differ ent than or-ing applications in that, the former are looking for the presence of or a condition of a preferred supply in order to switch to it. whereas true or-ing consists of a redundant n+1 co nfiguration with no preferred source. the following 2 circuits are simp le single isl6146 switchover circuits optimized for situations particular to the v batt and v ext voltages relative to each other. figure 50 shows an isl6146b switchover circuit where v ext , when present, is the preferred source and v batt could be lesser or greater than v ext . this circuit senses the presence of the preferred voltage supply to a programmable threshold level that when exceeded, v ext is passed to the output as v batt is disconnected from the output. r1 & r2 program the v ext level that must be preset for the preferred voltage to be passed to the output. q3 is necessary if v batt can ever exceed v ext to prevent current from flowing into v ext when present. the body diode of q3 q2 q1 gnd + - + c o m m o n p o w e r b u s + - + c o m m o n p o w e r b u s voltage dc - dc voltage dc - dc 3v-20v 3v-20v vout adj isl6146c flt uvlo ovp vin gate q4 q3 gnd vin gate vout adj isl6146c flt uvlo ovp figure 48. typical isl6146c application diagram q2 q1 gnd + - + c o m m o n p o w e r b u s + - + c o m m o n p o w e r b u s dc - dc voltage (1v-bias) vout adj isl6146a/b flt bias vin gate q4 q3 gnd vin gate vout adj isl6146a/b flt bias very low dc - dc voltage (1v-bias) very low en/en enabled signaled when distributed voltage >3v en/en enabled signaled when figure 49. controlled on/off application diagram
isl6146 20 fn7667.4 april 26, 2013 prevents that when q1 is on regardless of the v batt voltage. the isl6146 bias is pulled from the common drain node to ensure an always adequate bias from either source when the other is absent figure 51 shows operational sc ope shots of the above circuit. all of the scope shots were taken with a 5a load and 100f of bulk load capacitance. figure 52 is a isl6146a switchover circuit to use where the preferred v ext source is always greater than the v batt . because this is so, there is no need for a 3rd fet for blocking as in figure 50. additionally, the preferred v ext source when present or at a programmed minimum th reshold voltage via r1 and r2 divider will turn on q2/turn-off q1 but when absent or not minimally adequate, will do the opposite. in this circuit, with the isl6146a not connected to the battery, and thus no constant i vin load on it, which allows for longer battery life. bias voltage is pulled from the common output to ensure an always adequate ic bias from either source. figure 50. isl6146b external switchover schematic figure 51. external supply < batt supply connected figure 52. external supply < batt supply disconnected vin gate vout gnd adj isl6146b flt bias en q2 q1 switched output v ext 3.3v - 24v v batt 3.3v-20v q3 r1 r2 r3 use when v batt > v ext q3 disconnects v batt from output when gate is off. batt supply ext supply vout gate batt supply ext supply vout gate figure 53. isl6146a external switchover schematic figure 54. external supply > batt supply connected vin gate vout gnd adj isl6146a flt bias en q2 q1 switched output v batt v ext r1 r2 use when v batt < v ext batt supply ext supply vout gate
isl6146 21 fn7667.4 april 26, 2013 isl6146 evaluation platforms description and use of the evaluation boards the three isl6146 evaluation boards are used to demonstrate the four application configuratio ns discussed earlier. all the boards have adj shorted to vout with the pcb layout having the component footprints to insert a resistor of choice between adj and gnd to adjust the hs comp vth. likewise, the vin is connected to bias but these can be separated to provide an adequate bias voltage when or-ing <3v supplies or if providing a separate from vin voltage to bias. the isl6146aeval1z is configured to have a 8.5v minimum turn-on threshold with a 1.2v hysteresis. the isl6146beval1z is configured as a minimally featured maximum performance or-ing fet controller for 3v to 20v. the isl6146ceval1z is configured to operate with a 10.8v lower turn on threshold and 14.9v upper turn-off threshold. all three boards are equipped with 50a capable fets for high current evaluations and with a minimum of v in and v out bulk capacitance likely to be found in any power system design. after determining the bias source along with v in voltage criteria and configuring the evaluation board if necessary, for the application to be evaluated the board is ready for power. apply the bias voltage first (via the test points labeled bias), if separate from vin, then the v in voltage. monitor the provided test points for device performance with current loads up to 50a. figures 56 through 61 illustrate the three isl6146 evaluation boards for the three typical a pplications in photograph and schematic form. there are also 2 mini development boards named isl6146deval1 and isl6146eeval1. these boards are provided as a matching pair of either the isl6146d or isl6146e part type directly from the websit e or with either the isl6146a or isl6146b installed from the factor y (contact support if desired). the small size (1? x 0.5?) is suitab le for adding into an existing circuit using another or-ing fet controller. these small and simple boards have only the necessary components for its implementation utilizing the already present mosfet(s) in the circuit it is being added to. the mini evaluation circuit is designed to give the user the flexibility in either defaulting or signaling the enable on or to use a vin voltage threshold to turn-on the ic function. provided are access to the ic vin, gate and vout pins for best practices connections to the mosf et(s) along with adjustable hs vth via the adj pin and the fault output. the mini evaluation circuit is documented in figures 62 & 63 and table 2. figure 55. external supply > batt supply disconnected batt supply ext supply vout gate
isl6146 22 fn7667.4 april 26, 2013 figure 56. isl6146aeval1z figure 57. isl6146aeval1z schematic figure 58. isl6146beval1z figure 59. isl6146beval1z schematic
isl6146 23 fn7667.4 april 26, 2013 figure 60. isl6146ceval1z figure 61. isl6146ceval1z schematic figure 62. isl6146deval1z figure 63. isl6146edev1z schematic (mini-eval) dimensions are 1? x 0.5? (25.4mm x 12.7mm)
isl6146 24 fn7667.4 april 26, 2013 table 2. isl6146xevalz bom reference designator value description manufacturer part number isl6146aeval1z u1, u2 isl6146a or-ing fet controller intersil isl6146afuz q1, q2, q11, q12 30v, 50a fet various r1, 11 66.5k ? res, smd, 0603, 1% generic r2, r12, r6, r16 4.99k ? res, smd, 0603, 1% generic r3, r13 10 ? res, smd, 0603, 1% generic r4, r14 0 ? res, smd, 0603, 1% generic r5, r15 dnp res, smd, 0603, 1% generic r7, r17 10k ? res, smd, 0603, 1% generic c1, c11, c5 c15 100f alum. elect smd cap generic c2, c3, c12 c13 1f cap, smd, 0603, 50v, 10% generic c4, c14 dnp cap, smd, 0603, 50v, 10% generic tpx test point generic jx banana jack generic isl6146beval1z u1, u2 isl6146b or-ing fet controller intersil isl6146bfuz q1, q11 30v, 50a fet various r4, r14 4.99k ? res, smd, 0603, 1% generic r1, r10 10 ? res, smd, 0603, 1% generic r2, r12 0 ? res, smd, 0603, 1% generic r3, r13 dnp res, smd, 0603, 1% generic r5, r15 10k ? res, smd, 0603, 1% generic c1, c11, c5 c15 100f alum. elect smd cap generic c2, c3, c12 c13 1f cap, smd, 0603, 50v, 10% generic c4, c14 dnp cap, smd, 0603, 50v, 10% generic tpx test point generic jx banana jack generic isl6146ceval1z u1, u2 isl6146c or-ing fet controller intersil isl6146cfuz q1, q2, q11, q12 30v, 50a fet various r1, 11 93.1k ? res, smd, 0603, 1% generic r2, r12 1.4k ? res, smd, 0603, 1% generic r3, r13 4.53k ? res, smd, 0603, 1% generic r4, r14 0 ? res, smd, 0603, 1% generic r5, r15 dnp res, smd, 0603, 1% generic r6, r16 4.99k ? res, smd, 0603, 1% generic r7, r17 10k ? res, smd, 0603, 1% generic c1, c11, c3 c13 100f alum. elect smd cap generic c2, c12 1f cap, smd, 0603, 50v, 10% generic tpx test point generic jx banana jack generic
isl6146 25 fn7667.4 april 26, 2013 isl6146deval1z u1 isl6146d or-ing fet controller intersil isl6146dfuz r1, r2, r3 dnp res, smd, 0603, 1% generic r4 4.99k ? res, smd, 0603, 1% generic r5 10k ? res, smd, 0603, 1% generic c1, c2 1f cap, smd, 0603, 50v, 10% generic isl6146eeval1z u1 isl6146e or-ing fet controller intersil isl6146efuz r1, r2, r3 dnp res, smd, 0603, 1% generic r4 4.99k ? res, smd, 0603, 1% generic r5 10k ? res, smd, 0603, 1% generic c1, c2 1f cap, smd, 0603, 50v, 10% generic table 2. isl6146xevalz bom (continued) reference designator value description manufacturer part number
isl6146 26 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7667.4 april 26, 2013 for additional products, see www.intersil.com/product_tree about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change april 3, 2013 fn7667.4 added isl6146deval1z and isl6146eeval1z re lated information. figurers 62 and 63. corrected labels in figure 61. september 27, 2012 fn7667.3 added tape and reel parts to ordering information table for isl6146a/b/c/d/e products. thermal information - removed pb-free reflow link june 18, 2012 fn7667.2 added isl6146d and isl6146e. references to these products added throughout the datasheet. added figures 45 & 46 to illustrate the fault differences between is l6146a/b and isl6146d/e. moved figure 50 and revised the related text on page 20 before the evaluation board section. added figures 51 - 55 and related text on page 20 to page 21. february 27, 2012 fn7667.1 removed note ?msop packaged parts to be released soon? from ?ordering information? on page 3. added figures 42 & 43 on page 15. december 16, 2011 fn7667.0 initial release
isl6146 27 fn7667.4 april 26, 2013 package outline drawing l8.3x3j 8 lead dual flat no-lead plastic package rev 0 9/09 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" typical recommended land pattern top view side view c 0 . 2 ref 0 . 05 max. 0 . 00 min. 5 3.00 a b 3.00 (4x) 0.15 6 pin 1 index area pin #1 index area 6x 0.65 1.64 +0.10/ - 0.15 8 1 8x 0.400 0.10 6 max 1.00 see detail "x" 0.08 0.10 c c c ( 2.80 ) (1.64) ( 8 x 0.30) ( 8x 0.60) ( 2.38 ) ( 1.95) 2.38 0.10 8x 0.30 a mc b 4 2x 1.950 +0.10/ - 0.15 (6x 0.65) 4 5 pin 1
isl6146 28 fn7667.4 april 26, 2013 package outline drawing m8.118 8 lead mini small outline plastic package rev 4, 7/11 detail "x" side view 2 typical recommended land pattern top view pin# 1 id 0.25 - 0.36 detail "x" 0.10 0.05 (4.40) (3.00) (5.80) h c 1.10 max 0.09 - 0.20 33 gauge plane 0.25 0.95 ref 0.55 0.15 b 0.08 c a-b d 3.00.05 12 8 0.85010 seating plane a 0.65 bsc 3.00.05 4.90.15 (0.40) (1.40) (0.65) d 5 5 side view 1 dimensioning and tolerancing conform to jedec mo-187-aa plastic interlead protrusions of 0.15mm max per side are not dimensions in ( ) are for reference only. dimensions are measured at datum plane "h". plastic or metal protrusions of 0.15mm max per side are not dimensions are in millimeters. 3. 4. 5. 6. notes: 1. 2. and amsey14.5m-1994. included. included. 0.10 c m

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